EDA News H' Monday March 24, 2003 From: EDAToolsCafe _____ CareersCafe.com _____ About This Issue H' EDA in Taiwan & China Monitoring trends in emerging EDA markets _____ March 17-21, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Before we started to discuss the EDA market in Taiwan and China (PRC), Dataquest's Nancy Wu asked to set the stage for our discussion by describing the current state of affairs in the two countries with regards to semiconductor design, manufacturing, and test. After she set the stage, she then described the distinctions between the EDA market in Taiwan and China - with emphasis on China. Her concise and informative comments are as follows, and reflect highlights from a significant Dataquest report published in January 2003, co-authored by both Nancy Wu and Gartner/Dataquest analyst Gary Smith. "We started looking at the specifics of the EDA market in Taiwan and China in 2001 in a joint study done with EE Times-Asia. We surveyed close to 1000 engineers across the two countries about EDA tool usage in their daily work. We wanted to understand the nature of their engagements in ASIC, FPGA, and PCB design, and other types of design as well. And in that survey, we discovered a lot. And now we've updated the study. We had been seeing the Asia/Pacific market as the highest growth market in EDA over the past 5 years. Back in 1998, we had seen Taiwan emerge as the number one EDA marketplace in Asia, replacing Korea - which up to that point had been the number one market in Asia. But by 2000/2001, we were starting to hear that China was also becoming an EDA marketplace and that China was moving aggressively into [all aspects of] the semiconductor market. A balancing act Interestingly enough, the Chinese strategy has been, not just to attack the semiconductor manufacturing and test areas, but also to attack the design area as well. The Chinese approach [might have been] to copy what Taiwan had done previously - to start with manufacturing and test, and then move into design when both manufacturing and test capabilities were steady and strong - but the Chinese have clearly moved into design simultaneously with manufacturing and test. They've tried to get up to speed in the three different areas at the same time, so their approach has been [distinctly] different from what we've seen in Taiwan. Since 1998, as Taiwan has become the leading Asian EDA market, Taiwan has shared a 'bit' of that market with China. However, as I said earlier, now we're seeing China with more than just a 'bit' of the market. [In fact], although the EDA market in Taiwan continues to grow steadily, it's actually not growing as fast as that of China and India. We're seeing the design presence moving from Taiwan - and other traditional centers of design strength such as Singapore and Korea - and gradually shifting to China and India. [Parenthetically], I do sometimes hear of concerns from India, that China may be getting more attention [from the EDA industry] than India. However, my work has mostly been focused on China - and the market competition between Taiwan and China - so I do not know enough about India to comment in depth about that. [Meanwhile], we know that, in Taiwan, there are lots of OEMs who have [struck] deals with big computer giants like HP, IBM, Dell, and Compaq, among others - and those OEMs are supporting a type of derivative design [intended] to carry some of the design [load] for those large companies. That's really part of the reason why Taiwan has become so involved in design. [Additionally], we were interested to learn that the majority of the design projects in Taiwan have been engaged in producing computer peripherals and consumer electronic products. Alternatively, in China [in its brief history in design], most designs are dedicated to telecom and datacom end-users. Since China got into the design market later - when the market was hot for cell phones, PDAs, etc. - they've entered the design market from the point of telecomm, WAN, and sometimes even military [end-use type products]. Meanwhile, Taiwan continues to emphasize computer peripherals and consumer electronics-related design. A year ago, Gary Smith and I both spoke at a CMP Media event in China. We found there, that Taiwan does not believe that the design community in China is getting ahead of them - that Taiwan is still way ahead. And I think they may be partially right. [Of course], in the areas of manufacturing and test - companies in Japan, North American, and Europe continue to invest heavily in Taiwan - and now some in China as well. But those companies are also investing money in design, both in Taiwan and in China - and China is [quickly] becoming an even more interesting area than before. Meanwhile, lots of Taiwanese companies are [also] investing in China. They are either investing [by way of] new companies or setting up operations of exiting Taiwanese companies in China. [Yet], those Taiwanese investors don't see companies in China getting into the high-end design area. And, even though our survey indicates that companies from Japan, North America, and Europe are supporting design efforts in China that include high-speed, high-end design - even designs with greater than 10 million [on-chip devices] - Taiwan doesn't seem to see any need for concern. China does have local design engineering [talent] - graduates from local engineering schools capable of doing high-end design. The problem is that there's too much demand, and yet there aren't enough well trained engineers. [So] there's a lot of work going on in the local universities in China to train more engineers, to establish training facilities, and to cooperate with various EDA vendors to provide that training. China is [beginning to] emphasize getting more complex design projects into the schools, making them available to students, and also making more [on-the-job] training available to engineers who are already working. So China is working both in the universities and in industry [to promote the designer talent pool]. Price point [Meanwhile], design engineers - whether in Taiwan, China, or anywhere else in the world - want EDA tools that can help them with their work. And they must find the best price for the tools that will provide exactly what they need. A lot of considerations need to be taken into account before a purchase decision is made. These considerations have to be carefully [evaluated] before a designer buys and uses a tool to get a product out [the door]. Lots of tools are needed which are capable of dealing with complex designs - but these tools are extremely expensive. That's true every where in the world, no matter where [EDA tools] are sold. Suggestions that cultural distinctions in either the Taiwanese business environment or the Chinese business environment influence the way EDA vendors pursue customers in those countries are inaccurate. In Taiwan and China, [just like in every other EDA market], it's the price point and customer support which are far more important [for the EDA customer] than the particular culture surrounding the business relationship. Pricing concerns are [always] the major issue in getting EDA products to sell - particularly in China. If you think of the price point - and remember that China is getting into design a lot later, the cost of living is lower, the engineering costs are relatively inexpensive - and if you think of spending $500,000 on a synthesis tool, it's really more than Chinese designers can afford. Chinese design [houses] have to think of their ROI and how many projects they must engage just to cover the costs of purchasing such an expensive tool. Meanwhile, very few EDA tools are being translated into the local languages in either Taiwan or China. For Chinese design engineers who have started to focus in the design area, they are comfortable working in English and it's not necessary for the tool vendors to translate the tool [interface] or the documentation. Again, the biggest concern for these customers is not so much the language, as the price point of the tools. Market opportunity I think EDA vendors are trying to open the market in China - one or two of the vendors are giving super high discounts just to get into the Chinese market. These vendors want to have at least 'someone' who can use their tools [on a design team] and who can become familiar with the product and its capability. Those vendors feel that once they have that 'someone,' they'll then launch their product officially and be able to accomplish a larger market in China. [Today], vendors are competing to get the most market share by offering deep discounts - and then they will worry about how to get the revenue out of that market. [Certainly] in Taiwan, there's still price competition among the EDA vendors, but it's not [anywhere near] the level of price point that is being offered in China. [Additionally], since Taiwan has been engaged in design for many years - getting started much earlier than in China - they're familiar with the vendors and which vendor can provide which functions and at which price point. This is not happening broadly across China, [however], since the design market there has only become [a reality] in the last two to three years. [In fact], the EDA vendors have just started to launch their programs in China and lots of vendors are not selling into that market at all. So the local design communities in China don't [even] know which vendors are out there. What the Chinese design community needs to know, [today], is who is out there and who can help them do their designs. [Certainly], the Chinese know Synopsys, Cadence, Mentor and maybe another 10 vendors out of the top EDA companies. But it's not like in the North American design community, where those designers are aware of 50 to 60 percent of the [EDA] companies. It's going to take some time for the engineers in China to know who's out there - the EDA vendors need to promote their tools and get their names out there in China. For many EDA companies, particularly the start-ups in North America, it's really a business decision. Many of those start-ups are still in the design phase of their own tools - maybe they can sell one or two of their point tools to large North American customers [or customers in Japan or Europe], but those small companies aren't able, or ready, to move into emerging markets like China. [As always], it takes quite a while for a small [EDA] start-up to get into the market anywhere. For mid-size companies, however - those who have established a steady business and are able to remain financially stable, even during the downturn - those are the companies who should be capable of sustaining exploration into new areas. [Meanwhile], piracy is [always] a concern in emerging markets, particularly in China. For instance, we're seeing certain vendors who have a higher percentage of tool usage rates in China than [should be expected] when compared to their reported sales. The question is - Where are those engineers getting access to that software? [Not surprisingly], several vendors have seen that piracy is an issue and they've [noted] wide spread use of their tools. Do the vendors worry about it? They tell us - no, they do not. They say - yes, it's a concern to them, but what can they do? One vendor has told us that they're happy to see this wide spread use of their tool, because at least it's opening the market for them. They feel that they will get maintenance fees for the [pirated] software and they'll be able to keep relationships with those design houses [where the pirated software is being used]. Those vendors believe that, as those design houses get bigger, they will ask for more software seats and will end up paying for those seats eventually. [Clearly], the EDA market in China is small now, but it's growing much faster than other areas around the world. That is part of the reason why a lot of tools have been pirated. But, in general, those pirated tools are the lower-end tools. Users are not really able to copy the high-end tools, because they need training and support to use those high-end tools and to work around the bugs. [Again], it appears that for some EDA vendors - those who are engaged in providing the next-generation design tools - they are happy to see that there are lots of users out there and happy to think that someday those users will migrate to the need for the next generation of tools. Politics across the Taiwan Straight Taiwan and China have had a tense relationship for a long time. Gradually, however, they're moving closer to each other. You can't expect that leap to happen quickly and there are so many restrictions that must be lifted [by both governments] to allow joint [business development]. There is a lot of effort going on in the commercial area [to lower the barriers] - people in both countries lobbying their governments to open up to each other. China has always felt that Taiwan is part of their country, so China's approach is pretty much to welcome any investment from Taiwan on the mainland. [However], Taiwan is at the opposite end of that philosophy - they're still trying to maintain a distance from China, to educate their people that China is the 'other' country, [to insist] that Taiwan won't talk to China until Taiwan is accepted as an independent country. So the two governments come at the problem from very different standpoints. Taiwan has certain rules, for instance, about how much you can invest in China in a particular year. But, [as with everything], there are always tricks to get around those kind of rules. Large companies like TSMC and UMC are always under the spotlight [from the government of Taiwan], so it's not easy for them. But small and middle-sized companies can get around the rules and know that the government won't see that they're [working outside the rules]. [Meanwhile], businessmen on both sides of the Straight continue to try to reduce the barriers to joint ventures. Major centers of design Geographically, in Taiwan Hsin-chu is still the major design area. Tai-nan is in the southern part of the island, but that [technology center] is still under development, so there's not a lot of design effort going on there as yet. In China, there are actually a lot of different cities and provinces engaged in various types of design work including Guangdong, Shanghai, Beijing, Jiangsu, Zhejian, Sichuan, and Shandong - where Shanghai and Beijing are the most significant cities in design with the largest number of designers engaged in different types of design. Currently, there is only one major EDA show in China - EDAT Expo, Electronic Design Automation & Test Expo - that focuses on EDA. [EDA&T was held in early March 2003, in Shanghai and Beijing.] ASP-DAC, for instance, never happens in Taiwan or China. There are other shows in Taiwan and China - but they have much more emphasis on manufacturing, not on design." In closing Previously Nancy Wu worked as a securities analyst in Taiwan and also served in various capacities at Avanti. In closing, she said that Dataquest is "the best place I've ever worked." When asked about Gary Smith's on-going interest in Taoism, she said, "Not only has he studied the philosophy closely, but he practices it as well. That," she added with a smile, "is great for me, because he's my boss." Industry News - Tools & IP Cadence Design Systems, Inc. announced that Wintegra has deployed the Cadence Encounter digital IC design platform in Wintegra's WinPath Access packet processor. WinPath is a family of single-chip products to process 20+ protocols simultaneously on-chip for access networks. Circuit Semantics, Inc. (CSI) announced DynaCell-SI, an automated characterization and modeling tool for signal integrity verification of cell-based digital ICs, including both ASIC and COT flows. The company says the DynaCell-SI provides information required by signal integrity analysis tools to verify the level of tolerance of a design to the effects of noise and the impact on performance. DynaCell-SI identifies the functionality of a cell, generates comprehensive, non-redundant vector stimuli for characterization, characterizes the cell for noise using SPICE simulation, and generates a library model based on Synopsys' open Liberty library standard. The product requires the SPICE netlist and process model for each cell as input, as well as user information on desired ranges for glitch heights and widths, voltages, and output loads. LogicVision, Inc. announced that Oak Technology has selected LogicVision's Validator desktop silicon debug station for at-speed debugging of its IC designs integrated with LogicVision's embedded test technology. Alex Sinar, Vice President of Operations for Oak's TeraLogic Group, said, "Oak Technology is seeing strong demand for highly integrated SoCs for HDTV. The unique combination of LogicVision's Embedded Test technology and the Validator enables us to perform at-speed debug of our multi-million gate chips in days instead of weeks and pinpoint manufacturing yield hazards for rapid analysis and corrective action." Monterey Design Systems announced it will demonstrate the company's suite of IC design planning, physical synthesis and prototyping, and physical implementation products at the China International Semiconductor and Integrated Circuit Exhibition & Seminar 2003 on March 24th through 26th in Shanghai, China. Mentor Graphics Corp.'s Accelerated Technology Embedded Systems Division announced a version of the Nucleus RTOS for developers using the OMAP platform from Texas Instruments (TI). The company says that Nucleus developers familiar with ARM programming can now create a range of software applications for multimedia-enhanced devices using TI's OMAP application processors that contain an ARM processor application-programming interface. They add that developers can extend their application by using various Nucleus products including a TCP/IP networking suite, graphics package, and file management system. Novas Software, Inc. announced that NEC Micro Systems, Ltd. has signed a multi-year, volume purchase agreement for the Novas Debussy Debug System. NEC reports that it first deployed Debussy three years ago as the company's standard IC debug tool. Novas says this new contract confirms Debussy as the preferred debug platform for NEC's development of advanced LSI components, ASIC devices, and SoCs. ReShape, Inc. announced the company is making an entrance into the EDA industry with the introduction of what the company describes as "the industry's first full-chip implementation system that builds production layouts of multi-million gate SoCs in 24 hours or less." ReShape's GDS Builder is intended to leverage customers' investments in commercial physical design tools from Synopsys, Cadence, and Mentor Graphics, and to perform full-chip placement, routing, and analysis for complex designs. The company reports that they have used GDS Builder internally in their own design services work to complete nine commercial tape outs to date, and have used hierarchical layouts to achieve density and performance levels that match the quality of results they had previously achieved using traditional flat design techniques. GDS Builder combines a hierarchical chip implementation process with the company's Action Oriented flow to build design blocks in parallel on Linux servers. GDS Builder uses a layout technique called "channel-less block abutment" to meet requirements for small die size, low latency, and high signal integrity. The company says that production use of GDS Builder has demonstrated the following advantages over traditional scripted design methodologies - "Two weeks to first full-chip build, fast iterations, instant verification, and fast, predictable tape-outs" The company also reports that the last six tape-outs from GDS Builder were completed in 16 days or less, allowing the physical design team to proceed in parallel with the front-end design team. David Gregory, President and CEO of ReShape and co-founder of Synopsys, said: "This is the first time since the introduction of commercial logic synthesis more than 15 years ago, that we've had a major breakthrough in both the chip design process and in designer productivity. Full-chip implementation is currently taking even the best design teams more than three weeks to complete; other teams take up to eight weeks. Our automation techniques take this down to 24 hours, so design teams can build the chip over and over to get actual results, not just estimates. This can mean the difference between success and failure for a chip design." GDS Builder will be available at the end of Q2 2003. Synopsys, Inc. announced that Semiconductor Manufacturing International Corp. (SMIC) has chosen Synopsys' Galaxy Design Platform as the reference flow for its deep-submicron processes. James Sung, Vice President of Sales and Marketing at SMIC, said: "SMIC's strength in developing advanced silicon technologies in China, coupled with Synopsys' leadership in design automation software tools, provide strong benefits to our mutual customers." SMIC is described as China's "leading pure-play commercial IC foundry and the first to achieve volume production in eight-inch wafers with 0.35-micron, 0.25-micron, and 0.18-micron processes." SMIC is a Cayman Islands company based in Shanghai. The foundry provides design services, mask manufacturing, wafer fabrication, and testing capabilities. Also from Synopsys - The company announced an agreement with the High Technology Research and Development Center (HTRDC) of the Chinese Ministry of Science and Technology (MOST) to donate IC design tools to the center. The agreement also includes the purchase of additional Synopsys tools by MOST. The company says that Synopsys tools will be used to support the construction of IC design incubators in seven regions where major IC design industry development is occurring, including Shanghai, Beijing, Xi'an, Chengdu, Hangzhou, Wuxi, and Shenzhen. Synopsys says it has been helping to accelerate the growth of the China IC design industry since 1995 with a long-standing commitment to the region. MOST reports that it has been working since early 2000 to organize and implement a project for complex IC design through the HTRDC and the "863" IC Expert Group. The core of the project is an incubator program for IC design companies. Under the agreement with Synopsys, the HTRDC and the "863" IC Expert Group will endorse and standardize an IC design flow based on the licensed Synopsys tool set. Companies participating in the incubator program can use the Synopsys design flow to develop and implement designs. Jichun Feng, Director of the HTRDC said, "MOST's goal is to foster the growth of IC design companies and the IC design industry in China by providing an environment that aids small start-ups and encourages the ongoing development of design talent and innovative ideas within China. The agreement with Synopsys demonstrates the great progress we are making to accelerate the development of incubators in China's key centers of IC design." The HTRDC was founded in 1994 and has been approved by the Central Organization Committee of China. It serves various functions, including promoting international cooperation, researching various issues concerned with the industrialization of high and new technology, and developing strategy and policy for high-tech R&D. The HTRDC also provides project management, administration, statistical analysis and technology transfer for the "863" program, as well as consultation and services for MOST in matters pertaining to legal and intellectual property rights. From Synopsys as well - The company announced that the Information and Communication Networks Division (ICN) of Siemens used Synopsys Physical Compiler to tape out the Switching Element SE9, a complex ASIC designed for extremely fast switching of asynchronous transfer mode (ATM) cells. The first application for the SE9 is in the mobile switching fabric of the ICM Division. Siemens ICN used Physical Compiler's unified synthesis and placement to generate a placed and optimized netlist. LSI Logic, a Siemens ASIC vendor, accepted this placed netlist and completed the design. One final note from Synopsys - The company, along with Lightspeed Semiconductor announced that the two companies have signed a joint technology development agreement to provide support for Lightspeed's 0.13-micron Luminance family of Modular Array ASIC devices. Under the terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software, optimized to Lightspeed's Luminance devices. Lightspeed will distribute Synplicity's Synplify ASIC .sel library and accept Synplify ASIC netlists and timing analysis results as input to Lightspeed's back-end place-and-route tools. Coming soon to a theater near you DAC Panels - Conference organizers have announced various hands-on tutorials that will, once again, be available at the show in Anaheim, June 2nd to June 5th. The tutorials will emphasize "Signal and Power Integrity Analysis and Methodology" and will allow attendees to solve specific design challenges through guided hands-on experience using current tools and methodologies. Each tutorial focuses on a specific design challenge and encourages attendees to work with the tools, hands-on and in real time. All told there will be seven 3-hour tutorials, each limited to the first 30 enrollees with student-to-workstation ratios of 2:1. The following companies will be sponsoring various topics. Sequence Design will sponsor "What Is All This Noise about Signal and Power Integrity?" Cadence Design Systems, IOTA Technology, and Synplicity will sponsor "Signal and Power Integrity Analysis and Methodology." Sigrity will sponsor "Power and Signal Integrity Simulation of PCBs and Packages." Magma Design Automation will sponsor "Ensuring Signal and Power Integrity at Nanometer Technologies." Xilinx and Mentor Graphics Corp. will sponsor "3.125 Gbps with Your Hair on Fire: Simulation-Based Signal Integrity Analysis of Digital Interconnects at Multi-Gigabit Speeds." Apache Design Solutions will sponsor "Full-Chip Dynamic Power Grid Methodology from Planning to Verification." NPTest will sponsor "Signal and Power Integrity Validation with In-Circuit Measurements" ( www.dac.com ) FSA Smart Fabless Models Forum - The Fabless Semiconductor Association will present an intensive one-day program designed for executives in new and emerging companies on April 8th at the Santa Clara Convention Center. The event - "Design Productivity and Outsourcing" - will examine challenges all the way from design to outsourced manufacturing and product delivery. Conference organizers say that industry leaders will share their strategies for success in today's turbulent global market. Part I will focus on overcoming roadblocks to design productivity - tools, simulation, verification, design-for-manufacture, reusability, and more will be covered in this session. Part II picks up the development cycle at the handoff to manufacturing. Considerations in managing outsourcing while achieving rapid time-to-market will be addressed. Outsourcing manufacturing, supply chain management, and more will be included in the topics for discussion. Cadence's Penny Herscher will deliver the keynote address. ( www.fsa.org ) Newsmakers Applied Wave Research, Inc. (AWR) announced the company has named Tom Quan as Vice President of Marketing. Quan has 20+ years' experience, both technical and marketing, in the semiconductor and EDA industries. Previously, he was Vice President of Marketing at Cadence and also held management positions at Monterey Design Systems, Duet Technologies, and High Level Design Systems. Quan began his career at Intel Corporation as an IC designer. He holds a BSEE from the U.C. Berkeley, and an MBA from the Leavey School of Business at Santa Clara University. CiraNova, Inc. announced that James Solomon has joined the company's Board of Directors. Solomon was the EDAC Phil Kaufman award winner in 1997, and most recently has been involved in the founding of two companies - Xulu Entertainment, Inc. and Smart Machines Inc. Previously, Solomon founded SDA, which later became Cadence Design Systems. His most recent role at Cadence was forming the Analog and Mixed-Signal Division, where he held the position of Division President and General Manager. Earlier in his career, Solomon worked in design and design management capacities at National Semiconductor and Motorola Semiconductor. Solomon has a BSEE degrees and MSEE degrees from U.C. Berkeley. He is an IEEE Fellow and has published more than 50 technical papers. Solomon holds 23 patents. CiraNova is a venture-funded EDA start-up developing analog layout automation tools. Hier Design Inc. has announced that it is opening its doors in Santa Clara, CA, as the newest member of the EDA industry. Headed up by the energetic and articulate EDA veteran, Jackson Kreiter, who will serve as CEO and Chairman of the Board - the company "promises to obsolete ASICs with next-generation EDA software for FPGA design." The company says it will be providing software for high-speed FGPA designs, thereby serving a market which has been "overlooked by traditional EDA suppliers." Heir Design will launch their first software offerings in July 2003. Kreiter says, "The vast majority of designers are creating boards and FPGAs, not ASICs and systems on chip. We are building a company and product line to service the needs of the sophisticated FPGA designer community in a manner that will offer productivity and profitability - always the underpinnings of a successful EDA company." Heir Design's Board of Directors will include George Janac, founder of InTime and HLDS, Ping Chao, Founder of Silicon Perspective, Jonah Schnel of ITU Ventures, and Lucio Lanza of Lanza Tech Ventures. Kreiter's executive team will include Salil Raje as CTO and Vice President of Engineering, Pete Teshima as COO and CFO, Brian Jackson as Vice President of Business Development, and Dave Tarpley as Vice President of Business Development. Kreiter says he has done extensive research on the many technical and business aspects of creating a successful start-up, right from the get-go. Subsequently, he says he is extremely pleased with the experienced professionals that constitute his Board of Directors and Executive Team. Kreiter also reports that he is delighted to have EDA PR veteran Nanette Collins serving in the capacity of PR counsel for the newly formed company. VSIA, the Virtual Socket Interface Alliance announced the election of Michael Kaskowitz as the association's new president. Kaskowitz will serve in this voluntary capacity while maintaining his day job as General Manager of the Intellectual Property Division at Mentor Graphics Corp. Timothy O'Donnell, recently retired from ARM, is leaving the post as VSIA president, having held the position since June 2001. VSIA is an open, international organization with member companies from all segments of the SoC industry - system houses, semiconductor companies, EDA vendors, and IP providers. At the VSIA Board Meeting in February 2003, Kaskowitz, along with the VSIA Board and Staff began outlining the VSIA "Revitalization Plan" - also termed a "Re-energizing Plan" - with the goal of defining new programs to focus on the business issues of design reuse and SoC development, and renewing efforts to deliver more resources to VSIA's executive members. Kaskowitz announced that the association will form a taskforce from its member base to help define specific programs. Some examples of programs that have been discussed include - user groups to support more effective adoption of popular standards, executive and management level seminars and panels to provide a forum for exploring reuse issues, research projects and technical surveys to provide insights from VSIA end-user members, audio presentations on the website addressing both technical and business issues, as well as additional web-based and live events to allow VSIA to showcase industry insights, research, and results at the executive, management, and technical level. Tim O'Donnell said, "As GM of Mentor Graphics IP division, Kaskowitz has demonstrated an in-depth understanding of the technical and business issues critical to SoC success. His experience dovetails perfectly with our ongoing efforts to solve the tough problems that surround SoC development and the widening design gap. VSIA is fortunate to have a leader with such enthusiasm, strategic vision and relevant industry experience." Kaskowitz responded, "For the past few years, VSIA has focused exclusively on the Development Working Groups (DWGs) and we've done an excellent job producing more than 20 standards, specs, white papers and taxonomies in record time. Unfortunately, we have not done a good job of solving the problems of adoption, and of identifying and bringing to light the business issues of SoC and reuse. Our membership represents the most influential global reuse and SoC companies, and have tremendous insights into the business issues that companies struggle with in design reuse programs. We want to tap those resources and bring more value to our members." He added, "We want to create a series of Adoption Groups, which will be open to the entire VSIA membership, but which do not have to be 'not-for-profit.' Fees to join an Adoption Group may run from $15,000 to $20,000 and each group will be free to drive for adoption of a particular standard." He says that such a strategy will encourage like-minded companies within the association to work together towards a mutually beneficial goal, which in turn will enhance business opportunities for the companies and help to stimulate the economy. VSIA hopes to announce the formation of several Adoption Groups in the coming months. In the category of ... Doppler Effect Ms. Julia W. Howe - "He hath loosed the fateful lightning of his terrible swift sword." Gen. William T. Sherman - "War is hell." Dr. Richard P. Feynman - "What we need is imagination. We have to find a new view of the world." Mr. Gary Smith - "Almost all Westerners have a real hard time with the Taoist philosophy. We have the concept that 'we' have the only will. That unless 'we' do what 'we' want to do, nothing will happen. We have no concept of another higher will in action through us. Nothing happens unless we do something. The issue is, should that be done using man's will or a higher will. In the latter case, it's simply called the Tao. That's why the Zen Buddhists say that you will automatically know what to do once you have your satori. It's not that you don't do anything - it's that you follow the Tao, not your own will. Western culture has a Garden of Eden mentality. Our actions caused us to get kicked out, our actions are needed to get us back in. Eastern thought says that the world is perfect, we are in the Garden of Eden. We just are not awake enough to realize it. Western thought - the world is inherently bad and we have to fix it. Eastern thought - the world is inherently good and we need to get out of the way. That's why they tend to live in harmony with nature rather than to fight it." --Peggy Aycinena is a Contributing Editor and can be reached at peggy@ibsystems.com . You are subscribed as: [dolinsky@gsu.by]. Cafe News is a service for EDA professionals. EDAToolsCafe respects your online time and Internet privacy. If you would prefer not to receive this type of email or if you consider this message as unsolicited commercial e-mail, please click here . PLEASE NOTE: You can change the frequency of this newsletter by clicking here . If you have questions about EDAToolsCafe services, please send email to edaadmin@ibsystems.com . Copyright c 2002. Internet Business Systems, Inc. All rights reserved.